In recent years, the processing capability of a microprocessor has been improved in association with progress in the semiconductor manufacturing technology. As representative architecture for a microprocessor, there are the VLIW (very Long Instruction Word) and super scalar. The processor employing those architecture can simultaneously have a plurality of processing executed with a plurality of pipe lines. However, the processor based on pipe-line structure successively executes processing for each of the pipe lines, and for this reason, it is required to increase the number of pipe lines for processing instructions at a higher speed.
When an information processor executes instructions in a superscalar type of processor, for example, data on a main storage device is referred to as a source operand according a large number of instructions. As a system of generating a data address on a main storage device from each instruction, generally three values of a base register, an index register and displacement are added to each other.
Description is made herein for a conventional type of configuration of the processor. FIG. 16 shows block configuration of an information processor employing the system described above. In FIG. 16, an instruction CMD comprises OP (operand) code, a value RI indicating that a register number 1 is Operand 1, a value B2 indicating a base register number, a value X2 for an index register number, and a value D2 for displacement.
The information processor comprises, as shown in FIG. 16, a register file 91, latches 92, 93, 94, and an adder 95. The register file 91 reads a value B2 for a base register number as well as a value X2 for an index register number, and outputs the values to the latches 93, 94 each provided in the further latter stage.
The latch 92 reads a value D2 for displacement directly from an instruction CMD and outputs the value to the adder 95 at the next timing. The latches 93 and 94 read a value B2 for a base register number and a value X2 for an index register number from the register file 91 respectively and output the values to the adder 95 at the next timing.
The latch 92 directly fetches therein information for the instruction CMD, but the latches 93 and 94 fetch therein information for the instruction CMD via the register file 91. The adder 95 fetches therein all the values stored in the latches 2, 93 and 94 for addition and generates a data address on the main storage device.
Provided in the configuration shown in FIG. 16 are a pair (two units) of read ports for the register file 91 to one instruction CMD. When a plurality of instructions are to be simultaneously executed, processing may successively be executed by using the pair of read ports provided in the register file 91, but the processing is in turn delayed.
For this reason, in order to speed up the processing, it is conceivable that the number of pairs of read ports for the register file 91 are extensively provided according to the number of instructions to simultaneously be executed. If there are three instructions to simultaneously be executed, three pairs of read ports for the register file 91 may be provided therein. Provision of three pairs of read ports therein requires three data paths for reading registers. Description is made hereinafter for the configuration.
In order to execute processing for instructions at a high speed, in the information processor for simultaneously decoding and executing a plurality of instructions, it is one of solutions to provide the number of read ports for a base register as well as for an index register, said number equal to the number of instructions to be simultaneously decoded in the information processor, for adapting hardware thereof to execution of instructions in an ordinary instruction format with the configuration shown in FIG. 16.
FIG. 17 is a block diagram showing hardware configuration of the information processor based on the conventional technology. Configuration of latches is omitted in the information processor shown in FIG. 17 for simplifying description thereof. This information processor has instruction registers 96A, 96B, and 96C with instructions stored therein respectively. Instructions read out from the instruction registers 96A, 96B, and 96C are fetched in the register file 91. Namely, a value for a base register number as well as a value for an index register number are read out as a pair from the instruction registers 96A, 96B, and 96C respectively. For this reason, pipe lines number three times as many as that in the configuration shown in FIG. 16 are provided in a space between the instruction registers 96A, 96B, 96C and the register file 91.
The register file 91 has a register group 91A and selecting circuits 91B or the like. In this register file 91, assuming that the number of registers is n units (n: a natural number), data paths are required by a number obtained by multiplying the number of ports required for reading by n. Accordingly, the register group 91A and the selecting circuits 91B are connected to each other with required data paths.
Each of the selecting circuits 91B fetches a value for a base register number as well as a value for an index register number for each instruction read out from the register group 91A via a data path, selects each of corresponding adders 95A, 95B and 95C respectively, and outputs the values thereto.
The adder 95A corresponds to an instruction for the instruction register 96A, and adds all of three values for the base register, index register and displacement to each other to obtain a data address. The adder 95B corresponds to an instruction for the instruction register 96B, and adds all of three values for the base register, index register and displacement to each other to obtain a data address. The adder 95C corresponds to an instruction for the instruction register 96C, and adds all of three values for the base register, index register and displacement to each other to obtain a data address.
With the configuration described above, the number of read ports for the register file 91 shown in FIG. 17 is three times as many as that shown in FIG. 16. Accordingly, the register file 91 in FIG. 17 simultaneously reads out three instructions from the instruction registers 96A, 96B, and 96C. Namely, in the register file 91, when each value for a base register number and each value for an index register number are read out from the instruction registers 96A, 96B, and 96C respectively, each of the values is taken out from the register group 91A.
Then, each of the values read out from the register group 91A is sent to each of the selecting circuits 91B via the data path, and then is outputted to each of the adders 95A, 95B, and 95C respectively connected to the selecting circuits 91B for each instruction. In the adders 95A, 95B, and 95C, each of the values (a value for a base register number and a value for an index register number) received from the selecting circuits 91B and each value for a displacement, which is not shown, directly received from each of the instruction registers 96A, 96B, and 96C are added to each other. A result of the addition is a data address.
It should be noted that, as a technology similar to this type of technology, there are those, for example, disclosed in Japanese Patent Laid-Open Publication No. SHO 61-283930, Japanese Patent Laid-Open Publications No. HEI 3-245223, No. HEI 4-54638, and No. HEI 5-197547 in the same Publication.
By the way, as the conventional type of information processor speeds up a processing speed according to the number of instructions to simultaneously be executed by extensively providing the number of pipe lines and adders therein, the number of selecting circuits 91B for reading data from each register in the register group 91A increases in the register file 91, which causes increase in an amount of hardware as well as in a machine cycle as a result.
In the existing software, when simultaneously processing a group of instructions close to each other, generally an index register is not used (a register number is zero) , or there are many cases that the same index register is used for all the instructions. There has been thus desired, from the view point of a chip area and a machine cycle, a method of realizing simultaneous decoding and execution of a plurality of instructions without increasing the number of read ports for registers.